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Update IR

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IR commit: ab6ebce1cc25f7d2c634bd13af043f76d6ef524e
This commit is contained in:
Dmitry Stogov
2024-02-12 12:24:48 +03:00
parent a3620cd6e7
commit 2289af889c
3 changed files with 27 additions and 2 deletions
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2
ext/opcache/jit/ir/ir_aarch64.dasc
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@@ -2117,6 +2117,7 @@ static void ir_emit_sdiv_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
IR_ASSERT(shift != 0);
IR_ASSERT(IR_IS_CONST_REF(insn->op2));
IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
IR_ASSERT(def_reg != IR_REG_NONE && op1_reg != IR_REG_NONE && def_reg != op1_reg);
@@ -2173,6 +2174,7 @@ static void ir_emit_smod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
// uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
IR_ASSERT(mask != 0);
IR_ASSERT(IR_IS_CONST_REF(insn->op2));
IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
IR_ASSERT(def_reg != IR_REG_NONE && tmp_reg != IR_REG_NONE && def_reg != tmp_reg);

16
ext/opcache/jit/ir/ir_fold.h
View File

@@ -1608,6 +1608,22 @@ IR_FOLD(DIV(_, C_I64))
IR_FOLD_NEXT;
}
IR_FOLD(MOD(_, C_U8))
IR_FOLD(MOD(_, C_U16))
IR_FOLD(MOD(_, C_U32))
IR_FOLD(MOD(_, C_U64))
IR_FOLD(MOD(_, C_I8))
IR_FOLD(MOD(_, C_I16))
IR_FOLD(MOD(_, C_I32))
IR_FOLD(MOD(_, C_I64))
{
if (op2_insn->val.i64 == 1) {
/* a % 1 => 0 */
IR_FOLD_CONST_U(0);
}
IR_FOLD_NEXT;
}
IR_FOLD(DIV(_, C_DOUBLE))
{
if (op2_insn->val.d == 1.0) {

11
ext/opcache/jit/ir/ir_x86.dasc
View File

@@ -3787,6 +3787,7 @@ static void ir_emit_sdiv_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
int64_t offset = ctx->ir_base[insn->op2].val.u64 - 1;
IR_ASSERT(shift != 0);
IR_ASSERT(IR_IS_CONST_REF(insn->op2));
IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
IR_ASSERT(op1_reg != IR_REG_NONE && def_reg != IR_REG_NONE && op1_reg != def_reg);
@@ -3849,6 +3850,7 @@ static void ir_emit_smod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
uint32_t shift = IR_LOG2(ctx->ir_base[insn->op2].val.u64);
uint64_t mask = ctx->ir_base[insn->op2].val.u64 - 1;
IR_ASSERT(shift != 0);
IR_ASSERT(IR_IS_CONST_REF(insn->op2));
IR_ASSERT(!IR_IS_SYM_CONST(ctx->ir_base[insn->op2].op));
IR_ASSERT(def_reg != IR_REG_NONE && tmp_reg != IR_REG_NONE && def_reg != tmp_reg);
@@ -3868,8 +3870,13 @@ static void ir_emit_smod_pwr2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
ir_emit_mov(ctx, type, tmp_reg, def_reg);
}
| ASM_REG_IMM_OP sar, type, tmp_reg, (ir_type_size[type]*8-1)
| ASM_REG_IMM_OP shr, type, tmp_reg, (ir_type_size[type]*8-shift)
if (shift == 1) {
| ASM_REG_IMM_OP shr, type, tmp_reg, (ir_type_size[type]*8-1)
} else {
| ASM_REG_IMM_OP sar, type, tmp_reg, (ir_type_size[type]*8-1)
| ASM_REG_IMM_OP shr, type, tmp_reg, (ir_type_size[type]*8-shift)
}
| ASM_REG_REG_OP add, type, def_reg, tmp_reg
|.if X64