Compile the file separately and only include a header. There doesn't
seem to be a good reason to directly include the C file here, and
this ensures that there are no symbol clashes (see GH-7197).
* JIT/AArch64: Support shifted immediate
As pointed out by MikePall in [1], shifted immediate value is supported.
See [2]. For example, `add x0, x1, #4096` would be encoded by DynASM
into `add x0, x1, #1, lsl #12` directly.
In this patch, a helper is added to check whether an immediate value is
in the two allowed ranges: (1) 0 to 4095, and (2) LSL #12 on all the
values from the first range.
Note that this helper works for add/adds/sub/subs/cmp/cmn instructions.
[1] https://github.com/LuaJIT/LuaJIT/pull/718
[2]
https://github.com/LuaJIT/LuaJIT/blob/v2.1/dynasm/dasm_arm64.lua#L342
Change-Id: I4870048b9b8e6c429b73a4803af2a3b2d5ec0fbb
* Deprecatd CMP_IMM/ADD_SUB_IMM and add test cases
Macros CMP_IMM and ADD_SUB_IMM are deprecated and instead we use
this helper to guard the immediate encoding.
Add two 64-bit only test cases, since 64-bit integers are used
and tested inside.
Change-Id: I0b42d4617b40372e2f4ce5b6ad31a4ddb7d89e49
Rather than using def_info, check against the actual arg_info type.
As it is stored as a type mask nowadays, this is not much harder,
but more general and more robust as we don't need to deal with
inaccurate cases.
This test fails on s390x with opcache. Presumably the large allocation
works fine there as long as it's not used.
Switch to a different error condition that produces a more reliable
failure.
This issue is properly fixed by GH-7121 on master. For older
branches, disable the use of range information in SCCP, to
reduce impact of potentially incorrect ranges.
'tbnz/tbz' instruction can be used to check whether a given W or X
register value is negative or positive.
For example,
```
tst x0, x0
blt >1
```
can be optimized as `tbnz x0, #63, >1`
It's important to note that the jump range of 'tbnz/tbz' is limited, and
it's better NOT to use 'tbnz/tbz' if the target of 'b.cond' is a label
in section .cold_code or a global label, such as the instruction
sequence `tst RETVALw, RETVALw; blt ->trace_halt` at function
zend_jit_trace_exit_stub(), and the instruction sequence `tst REG0,
REG0; blt >7` at function zend_jit_incdec_obj().
Minor updates:
Use macros BW_OP_32_WITH_CONST and GC_ADDREF at function
zend_jit_push_call_frame().
Change-Id: I1597609bdabf55ea2f9d24528e7a037bc3e5c3a1
Updates the deprecation message for implicit incompatible float to int conversion from:
```
Implicit conversion from non-compatible float %.*H to int in %s on line %d
```
to
```
Implicit conversion from float %.*H to int loses precision in %s on line %d
```
Related: #6661
One shift instruction can be saved if 'shifted register' is used.
It's worth noting that the destination register of previous shift
instruction doesn't hold the shift result any longer now. And we have to
guarantee that 'shifted register' mode is applied to all the use sites
of this destination register.
Besides, several code-style issues are fixed.
Change-Id: I8bcdd092253d342d383732a926512e761e453808
The following warning message would be produced for macOS on Apple
silicon.
```
php-src/ext/opcache/jit/zend_jit_arm64.dasc:15356:79: warning: incompatible pointer types passing 'ptrdiff_t *' (aka 'long *') to parameter of type 'int64_t *'
(aka 'long long *') [-Wincompatible-pointer-types]
const char *name = zend_jit_disasm_find_symbol((ptrdiff_t)cp + offset - 4, &offset);
^~~~~~~
ext/opcache/jit/zend_jit_disasm.c:210:58: note: passing argument to parameter 'offset' here
int64_t *offset) {
^
```
Flag -Wincompatible-pointer-types is enabled by default in Clang [1],
but not in GCC [2].
Adding explicit type conversion would remove this warning.
[1]
https://releases.llvm.org/10.0.0/tools/clang/docs/DiagnosticsReference.html#wincompatible-pointer-types
[2]
https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Warning-Options.html#Warning-Options
Change-Id: Ia0777a5731ba8f0764e232c0d47aeaab076d13f5
- perform constant shift by single instruction
TODO: DynAsm: can't encode "lsl x0, x0, #var" !!!
- avoid usage of REG1 for variable shift (it was x86 limitation)
- enable register reuse for SL/SR instructions
- remove special scratch register handling for SL/SR (it was x86
limitation)
- Remove need for extra scratch registers. AArch64 JIT backend
don't use extra register for constants. It uses reserved TMP
registers.
George Peter Banyard