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Commit Graph

4171 Commits

Author SHA1 Message Date
Dmitry Stogov 2fabe2751c JIT/AArch64: Rename B_IMM26 into B_IMM. 2021-05-19 09:47:23 +03:00
Dmitry Stogov a6bb79f16d Correct DWARF frame description.
Now GDB correctly shows backtraces that involves JIT-ed code for
functional/tracing JIT, HYBRID/CALL VM, x86/AArch64 CPU.
(opcache.jit_debug=0x100 should be set).
2021-05-19 09:09:51 +03:00
Dmitry Stogov 767a4af2c7 Introduce and use ZEND_JIT_TARGET_X86 and ZEND_JIT_TARGET_ARM64 macros.
Remove x86 specific code from ext/opcache/jit/zend_jit_arm64.dasc.
Fixed ARM64 build without libcapstone.
2021-05-18 21:59:32 +03:00
Dmitry Stogov 5fe2062585 Correct DWARF frame description.
Now GDB correctly shows backtraces that involves JIT-ed code for
functional/tracing JIT, HYBRID/CALL VM, x86/AArch64 CPU.
(opcache.jit_debug=0x100 should be set).
2021-05-18 18:21:08 +03:00
Dmitry Stogov dae662ffbc Fixed zend_long_is_power_of_two/zend_long_floor_log2 mess 2021-05-18 15:32:36 +03:00
Dmitry Stogov d6d0b1c389 Remove unnecessary #ifdef 2021-05-18 15:32:36 +03:00
Dmitry Stogov f70ac416c3 Fixed possible failure when repair after overflow detection 2021-05-18 15:32:36 +03:00
Dmitry Stogov a69701de2e Fix "store to misaligned address" ASAN warnings 2021-05-18 15:32:36 +03:00
Dmitry Stogov d6bf98428d Fixed format specifier 2021-05-18 15:32:35 +03:00
Dmitry Stogov f15f01aed7 JIT/AArch64: disable register allocation for expected ++/-- overflow case.
This fixes ext/opcache/tests/jit/inc_021.phpt with tracing JIT.
2021-05-18 15:32:35 +03:00
Dmitry Stogov fc3157ea0f Generate veneers to perform long jumps.
This makes symfony_demo app working with -d opcacge.jit=1205.
(21 MB of JIT-ed code).
2021-05-18 15:32:35 +03:00
Dmitry Stogov 0e8fc156f8 DynASM/ARM64: Add abiulity to plug-in generation of veneers to perform long jumps. 2021-05-18 15:32:35 +03:00
Dmitry Stogov 59ef219994 Fixed ZTS build. 2021-05-18 15:32:35 +03:00
Dmitry Stogov 8970b684e9 Use symbolic labels for BL and ADR instructions 2021-05-18 15:32:35 +03:00
Dmitry Stogov e1e050d752 Use better code for trace exits. Don't store CPU registers that can't be used by deoptimizer. 2021-05-18 15:32:35 +03:00
Dmitry Stogov 43b138852e Remove unused TMP4. Use intra-precedure call scratch registers for TMP2 and TMP3. 2021-05-18 15:32:35 +03:00
Dmitry Stogov 78cdb2a7a0 Allow to print JIT assemble without binary addresses (opcache.jit_debug=0x001) and with (opcache.jit_debug=0x401) for both ARM and x86. 2021-05-18 15:32:35 +03:00
Dmitry Stogov 5dd539b866 Fixed JIT memory usage debug info (opcache.jit_debug=0x200) 2021-05-18 15:32:35 +03:00
Dmitry Stogov 94ce76a331 Implemented AArch64 support for GDB/JIT interface.
Stack frame description is not accurate, so backtraces that involved
JIT-ed code may be brocken. Disassemble and breakpoints on JIT-ed code
work fine.
2021-05-18 15:32:35 +03:00
Dmitry Stogov b5aa339cfd Reenable PROFITABILITY_CHECKS 2021-05-18 15:32:35 +03:00
Dmitry Stogov da2bed357a Fixed incorrect range check (missed sign bit) 2021-05-18 15:32:35 +03:00
Hao Sun 1a6bcd0f80 Fix commit 8143a49: macro ADD_SUB_64_WITH_CONST_32 should be used
"(struct.._offset+offsetof(zend_..struct, field))" might exceed the
range of ADD_SUB_IMM, leading to DynASM error DASM_S_RANGE_I for
ZTS+CALL test variant.

Using macro ADD_SUB_64_WITH_CONST_32 would fix it.

Change-Id: I3233cefbcd1ddea16e7de6725c2dc5ff43373916
2021-05-18 15:32:35 +03:00
Dmitry Stogov 44220c5380 Fixed incorrect stack size calculation (sizeof(zval) == 16) 2021-05-18 15:32:34 +03:00
Dmitry Stogov 0b79199500 Peephole Code Optimization:
ldr + sxtw -> ldrsw
lsl + add/sub/cmp -> add/sub/cmp (shifted register)
LOAD_64BIT_VAL + add -> ADD_SUB_64_WITH_CONST
2021-05-18 15:32:34 +03:00
Dmitry Stogov 00270c6c01 Use better code for prologue and fix code generaion for "return -1". 2021-05-18 15:32:34 +03:00
Dmitry Stogov 3014cf4add Fix compilation warnings 2021-05-18 15:32:34 +03:00
Dmitry Stogov ee08686f7c Fixed JIT failure on Zend/tests/bug43175.phpt ZTS build, CALL VM. 2021-05-18 15:32:34 +03:00
Hao Sun fd3f247bda Revert the macro uses for Z_TYPE_P(val) in commit 1fff62b
As suggested by Dmitry, macro CMP_32_WITH_CONST is not necessary because
Z_TYPE_P(val) is of uchar type and it can be encoded as the imm field of
'cmp' instruction directly.

Change-Id: Icb8f9ee847b9a08cb1e9127e7faf6c89d1431922
2021-05-18 15:32:34 +03:00
Dmitry Stogov 59622d9ff2 Fixed profile based JIT (opcache.jit=1225) 2021-05-18 15:32:34 +03:00
Hao Sun 2de4a93d21 Fix commit 6e344ed: temporary register should be kept for GET_ZVAL_LVAL
Macro GET_ZVAL_LVAL is optimized in commit 6e3443d, using 'reg' as the
temporary register. However, the assertion would fail for "jit=1205".

This patch reverts this optimization for GET_ZVAL_LVAL.

Change-Id: Iecb134fa9438ef993e6393974caa5710657a462e
2021-05-18 15:32:34 +03:00
Hao Sun 77ecce7a60 Use fewer temporary registers if possible
For macro "SAFE_MEM_ACC_WITH_UOFFSET* ldr/ldrb", the target register can
be used as temporary register to load the offset if needed. Hence one
temporary register is saved for macros LONG_CMP, GET_ZVAL_LVAL,
CMP_ZVAL_TYPE, IF_ZVAL_TYPE and IF_NOT_ZVAL_TYPE.

Change-Id: I43f35186cec9a4157bc73b1cae6643aa59140de2
2021-05-18 15:32:34 +03:00
Hao Sun 65b834a686 Improve macro LONG_ADD_SUB_WITH_IMM
Offset "Z_OFFSET(op1_addr)" might be loaded into temporary registers for
two times, i.e. by these two SAFE_MEM_ACC_WITH_UOFFSET respectively.

This patch removes this case.

Change-Id: Ib1fde9c9a39f6b5f1ca322dc27b0a9d9d51fbef0
2021-05-18 15:32:34 +03:00
Hao Sun b6e9259620 Remove the deprecated macros
Macros PUSH_BASE_ADDR, PUSH_ADDR_ZTS, GET_ZVAL_W2, SET_ZVAL_W2,
IS_32BIT, PUSH_ADDR and PUSH_ZVAL_ADDR are 32-bit platform dependent in
the x86 implementation, hence they are derepcated in AArch64.

Macro ADDR_OP1 is only used by PASH_* macros, and it is deprecated in
AArch64.

Macros MEM_OP3_3 and AVX_OP are platform dependent and they are not used
in AArch64.

Macro LONG_OP_WITH_32BIT_CONST is replaced with LONG_ADD_SUB_WITH_IMM.

Macro DOUBLE_OP is not used because we use temporary FP register to load
the value from address firstly and then conduct FP math operations with
the help of DOUBLE_MATH_REG.

Macro LONG_MUL is deprecated. MUL between two LONG values is implemented
in a different way from ADD or SUB mainly because extra temporary
register is needed in order to detect integer overflow. See function
zend_jit_math_long_long().

Change-Id: I249f28820aaa86c7638ecf3eee08f8750a232397
2021-05-18 15:32:34 +03:00
Hao Sun 4c6d317730 Use macros CMP_*_WITH_CONST if possible
Macros CMP_*_WITH_CONST were introduced in [1]. We revisit all the uses
of 'cmp' instructions with constants, and apply these macros if
possible.

[1] https://github.com/php/php-src/commit/66ba9af

Change-Id: Idd233cb9afba84dd106fcc5ee8bf5417d91989c7
2021-05-18 15:32:34 +03:00
Hao Sun 8c794128be Use ADD_SUB_IMM for macros ADD_SUB_*_WITH_CONST*
Macros ADD_SUB_*_WITH_CONST* were introduced in [1], but it would be
more accurate to use ADD_SUB_IMM even though ADD_SUB_IMM == CMP_IMM.

Regarding the definition of ADD_SUB_IMM, the comment is updated since it
is used to guard 'subs' and adds' instructions as well.

[1] https://github.com/php/php-src/commit/0609b97

Change-Id: I102ebbf626a438da061f6c01b01029807de1ff14
2021-05-18 15:32:34 +03:00
Hao Sun b019ffe59c Don't use TMP3 except ZTS
Currently temporary register TMP3 is used in particular for ZTS mode.
Hence it would be better not to use it in other sites except ZTS.

In this patch, the value in TMP1, i.e. "REG1 + IP", might be clobbered
and should be calcauted again.

Change-Id: I17434d4f4b8d6f1e71f49eadb42e06db975d7bbe
2021-05-18 15:32:34 +03:00
Dmitry Stogov 609c3bee2e 'lea' -> 'add' 2021-05-18 15:32:34 +03:00
Dmitry Stogov 7ece98f2f4 Use proper macro 2021-05-18 15:32:33 +03:00
Dmitry Stogov fc377742a6 Fix compilation warning 2021-05-18 15:32:33 +03:00
Dmitry Stogov 123df80d40 Use B/BL intead of BR/BLR if possible 2021-05-18 15:32:33 +03:00
Dmitry Stogov ce9d59a347 Imroved code for constants loading 2021-05-18 15:32:33 +03:00
Dmitry Stogov 6036d159fb Imroved code for CV initialization 2021-05-18 15:32:33 +03:00
Dmitry Stogov db25a6ed16 Use single instruction 2021-05-18 15:32:33 +03:00
Dmitry Stogov 38474a4144 Use less temporary registers 2021-05-18 15:32:33 +03:00
Dmitry Stogov 731456a68e Introduce ADD_SUB_64_WITH_CONST/ADD_SUB_64_WITH_CONST_32/ADD_SUB_32_WITH_CONST macros 2021-05-18 15:32:33 +03:00
Dmitry Stogov 1df56b2873 Introduce CMP_64_WITH_CONST/CMP_64_WITH_CONST_32/CMP_32_WITH_CONST macros 2021-05-18 15:32:33 +03:00
Dmitry Stogov 2c147fe5eb Optimize AArch64 code generator
- use cbz/cbnz for comparison with zero
- use xzr/wzr instead of #0 in mov/cmp
- use "subs" imstead of "sub x1,...; cmp x1, xzr"
- avoid loading immediate value to register when it may be direclu used
  as a source immendiate operand in ldr*/str*/add*/sub*/cmp
2021-05-18 15:32:33 +03:00
Dmitry Stogov 6b50c390a6 Improve code for MUL overflow detection (less instructions and less
temporary registers)
2021-05-18 15:32:33 +03:00
Dmitry Stogov 186a5277aa Don't optimize MUL into SHIFT if we have to check for overflow 2021-05-18 15:32:33 +03:00
Dmitry Stogov a1389a774c Skip 64-bit related tests on 32-bit platforms 2021-05-18 15:32:33 +03:00