One shift instruction can be saved if 'shifted register' is used.
It's worth noting that the destination register of previous shift
instruction doesn't hold the shift result any longer now. And we have to
guarantee that 'shifted register' mode is applied to all the use sites
of this destination register.
Besides, several code-style issues are fixed.
Change-Id: I8bcdd092253d342d383732a926512e761e453808
The following warning message would be produced for macOS on Apple
silicon.
```
php-src/ext/opcache/jit/zend_jit_arm64.dasc:15356:79: warning: incompatible pointer types passing 'ptrdiff_t *' (aka 'long *') to parameter of type 'int64_t *'
(aka 'long long *') [-Wincompatible-pointer-types]
const char *name = zend_jit_disasm_find_symbol((ptrdiff_t)cp + offset - 4, &offset);
^~~~~~~
ext/opcache/jit/zend_jit_disasm.c:210:58: note: passing argument to parameter 'offset' here
int64_t *offset) {
^
```
Flag -Wincompatible-pointer-types is enabled by default in Clang [1],
but not in GCC [2].
Adding explicit type conversion would remove this warning.
[1]
https://releases.llvm.org/10.0.0/tools/clang/docs/DiagnosticsReference.html#wincompatible-pointer-types
[2]
https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Warning-Options.html#Warning-Options
Change-Id: Ia0777a5731ba8f0764e232c0d47aeaab076d13f5
- perform constant shift by single instruction
TODO: DynAsm: can't encode "lsl x0, x0, #var" !!!
- avoid usage of REG1 for variable shift (it was x86 limitation)
- enable register reuse for SL/SR instructions
- remove special scratch register handling for SL/SR (it was x86
limitation)
- Remove need for extra scratch registers. AArch64 JIT backend
don't use extra register for constants. It uses reserved TMP
registers.
* JIT/AArch64: Code refactoring for macros
Update the comments and rename arguments for some macros.
The following macros are renamed:
SAFE_MEM_ACC_WITH_UOFFSET -> MEM_ACC_64_WITH_UOFFSET
SAFE_MEM_ACC_WITH_UOFFSET_32 -> MEM_ACC_32_WITH_UOFFSET
SAFE_MEM_ACC_WITH_UOFFSET_BYTE -> MEM_ACC_8_WITH_UOFFSET
MEM_STORE_BYTE_ZTS -> MEM_STORE_8_ZTS
MEM_STORE_ZTS -> MEM_STORE_64_ZTS
MEM_LOAD_ZTS -> MEM_LOAD_64_ZTS
MEM_LOAD_BYTE_ZTS -> MEM_LOAD_8_ZTS
ADD_IP_FROM_CST -> ADD_IP_WITH_CONST
The following macros are deprecated and removed:
SET_Z_PTR, GET_Z_W2, SET_Z_W2
Change-Id: I767cf70f373e5f5a1090079e70f8e953a654da00
* Use MEM_ACCESS_*_WITH_UOFFSET
It's more accurate to use "MEM_ACCESS_*_WITH_UOFFSET" than
"MEM_ACC_*_WITH_UOFFSET".
Change-Id: I71479a809008848b61c4786016e6c10110e6aa8b
* Revert the updates for macros ADD_IP_WITH_CONST and LONG_ADD_SUB_WITH_IMM
As pointed by Dmitry, (int32_t) (1LL << 32) would make the assertion
"TRUE", which is not expected by us.
Change-Id: I767cf70f373e5f5a1090079e70f8e953a654da00
Zero register, i.e. xzr, can be used directly to zero FP register.
TODO: FMOV from ZR may be slow on some cores and the preferred
instructio is MOVI with immediate zero [1]. However, MOVI is not
recoginized by DynASM/arm64.
[1] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=523d72071960
Change-Id: I0eaee4445e05adb45c6bb80ddb62ea02cdc9f4db
* JIT/AArch64: [macos][ZTS] Support fast path for tlv_get_addr
Access to TLV(thread local variable) in macOS is in "dynamic" form and
function tlv_get_addr() is invoked to resolve the address. See the
example in [1].
Note there is one struct TLVDescriptor [2] for each TLV. The first
member holds the address of function tlv_get_addr(), and the other two
members, "key" and "offset", would be used inside tlv_get_addr().
The disassembly code for function tlv_get_addr() is shown in [3]. With
the value from system register, i.e. tpidrro_el0, together with "key"
and "offset", the TLV address can be obtained.
Note that the value from tpidrro_el0 varies for different threads, and
unique address for TLV is resolved.
It's worth noting that slow path would be executed, i.e. function
tlv_allocate_and_initialize_for_key(), for the first time of TLV access.
In this patch:
1. "_tsrm_ls_cache" is guaranteed to be accessed before any VM/JIT code
during the request startup, e.g. in init_executor(), therefore, slow
path can be avoided.
2. As TLVDecriptor is immutable and zend_jit_setup() executes once, we
get this structure in tsrm_get_ls_cache_tcb_offset(). Note the 'ldr'
instruction would be patched to 'add' by the linker.
3. Only fast path for tlv_get_addr() is implemented in macro
LOAD_TSRM_CACHE.
With this patch, all ~4k test cases can pass for ZTS+CALL in macOS on
Apple silicon.
[1] https://gist.github.com/shqking/4aab67e0105f7c1f2c549d57d5799f94
[2]
https://opensource.apple.com/source/dyld/dyld-195.6/src/threadLocalVariables.c.auto.html
[3] https://gist.github.com/shqking/329d7712c26bad49786ab0a544a4af43
Change-Id: I613e9c37e3ff2ecc3fab0f53f1e48a0246e12ee3
zend_throw_error() and zend_error() are variadic functions. In Linux,
arguments are passed in registers, whereas they must be put on stack in
Macos [1][2].
In this patch:
1. preprocessor macro "__APPLE__" is used to distinguish the OS.
2. the third argument "CARG3" is the only variadic argument and put on
stack.
3. the invocation of zend_error() is converted back to regular call in
zend_jit_undefined_offset_stub() and zend_jit_undefined_index_stub().
With this patch, all ~4k test cases can pass for "nonZTS+CALL"
functional/tracing JIT with Macos Apple Silicion.
[1]
https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms#Overview
[2] https://github.com/below/HelloSilicon#listing-9-1
Change-Id: I49bc3233fc253ad3e77e8664464ff3e830dcd183
* PHP-8.0:
Fix register save/restore around calls. (This fixes ext/opcache/tests/jit/fetch_dim_rw_001.phpt with -d opcache.jit=1202 without PROFITABILITY_CHECKS)
1. Generate exit table at the end of each trace (list of unconditional branches for all side exit)
2. Jump to this table if conditional branch to side exit can't be performed because of limited jump distance (+/-1MB) (avoid extra veneers for side exits).
3. During trace linking, update targets of conditional branches to this exit table, if target trace can't be reachd because of limited jump distance (+/-1MB)
Dmitry Stogov